Serial peripheral interface (SPI) is a hardware/software communication protocol originally developed by Motorola and widely used by others in the industry. SPI is quite straightforward – it defines how to communicate in easy way between 2 digital devices – i.e. between AVR and devices, like other AVRs, external EEPROMs, DACs, ADCs, etc. SPI is a single-master communication protocol. This means that one central device initiates all the communications with the slaves. When the SPI master wishes to send data to a slave and/or request information from it, it selects slave by pulling the corresponding SS line low and it activates the clock signal at a clock frequency usable by the master and the slave. The master generates information onto MOSI line while it samples the MISO line.
The SPI bus logic signals
- SCLK – Serial Clock (output from master), alternative names: SCK, CLK.
- MOSI – Master Output, Slave Input (output from master), alternative names: SIMO, SDI(for slave devices), DI, DIN, SI, MTST.
- MISO – Master Input, Slave Output (output from slave), alternative names: SOMI, SDO (for slave devices ), DO, DOUT, SO, MRSR.
- SS – Slave Select (active low, output from master), alternative names: CS, Enable (EN), nCS, CSB, CSN, nSS, STE, SYNC.
SPI clock modes
The four modes combine two mode bits:
- CPOL indicates the initial clock polarity. CPOL=0 means the clock starts low, so the first (leading) edge is rising, and the second (trailing) edge is falling. CPOL=1 means the clock starts high, so the first (leading) edge is falling.
- CPHA indicates the clock phase used to sample data; CPHA=0 says sample on the leading edge, CPHA=1 means the trailing edge. Since the signal needs to stablize before it’s sampled, CPHA=0 implies that its data is written half a clock before the first clock edge. The chipselect may have made it become available.
In the SPI mode number, CPOL is the high order bit and CPHA is the low order bit. So when a chip’s timing diagram shows the clock starting low (CPOL=0) and data stabilized for sampling during the trailing clock edge (CPHA=1), that’s SPI mode 1. Note that the clock mode is relevant as soon as the chipselect goes active. So the master must set the clock to inactive before selecting a slave, and the slave can tell the chosen polarity by sampling the clock level when its select line goes active. That’s why many devices support for example both modes 0 and 3: they don’t care about polarity, and always clock data in/out on rising clock edges.
Props and cons of SPI versus I²C
Advantages of SPI
- Full duplex communication.
- Higher throughput than I²C protocol.
- Not limited to 8-bit words in the case of bit-transferring.
- Arbitrary choice of message size, contents, and purpose.
- Simple hardware interfacing.
- Typically lower power requirements than I²C due to less circuitry.
- No arbitration or associated failure modes.
- Slaves use the master’s clock, and don’t need precision oscillators.
- Transceivers are not needed.
- At most one “unique” bus signal per device (CS); all others are shared
Disadvantages of SPI
- Requires more pins on IC packages than I²C.
- No in-band addressing. Out-of-band chip select signals are required on shared busses.
- No hardware flow control.
- No slave acknowledgment.
- Multi-master busses are rare and awkward, and are usually limited to a single slave.
- Without a formal standard, validating conformance is not possible.
- Only handles short distances compared to RS-232, RS-485, or CAN.
Check out the Wikipedia page on SPI, which contains some good information on SPI.
This article presents a more correct way to set up an SPI network amongst your embedded devices (for more then one slave), i.e. pull-up resistors for CS and tri-state buffer for MISO.
Next great piece of information – summary of SPI – that I found among kernel docs.